Key Theoretical Concepts to Remember
Von Neumann Architecture vs. Harvard Architecture:
Von Neumann: Shared memory and bus for instructions and data. Suffers from the "Von Neumann Bottleneck."
Harvard: Separate physical memory and buses for instructions and data.
Instruction Cycle: Fetch $\rightarrow$ Decode $\rightarrow$ Execute $\rightarrow$ Store.
Addressing Modes:
Immediate: Operand is part of instruction (e.g.,
ADD 5).Direct: Address field contains effective address.
Indirect: Address field points to memory location containing the effective address.
Register/Register Indirect: Operations performed directly using CPU registers.
Memory Hierarchy (Fastest to Slowest): Registers $>$ Cache Memory $>$ Main Memory (RAM) $>$ Secondary Storage (Hard Disk / SSD).
Logic Gates & Digital Circuits:
Universal Gates: NAND, NOR.
Combinational Circuits: Adders, Multiplexers (Data Selector), Demultiplexers, Decoders.
Sequential Circuits: Flip-Flops (stores 1 bit of data), Counters, Registers.
1. Computer Architectures: Von Neumann vs. Harvard
The foundation of modern computing relies on how instruction memory and data memory are connected to the Central Processing Unit (CPU).
Von Neumann Architecture
Core Concept: Utilizes a single shared memory space and a single shared bus system for storing both program instructions and operational data.
Instruction Cycle: Fetch and data read operations must happen sequentially over the same physical bus.
The Von Neumann Bottleneck: Because instructions and data share the same communication bus, the CPU cannot read an instruction and read/write data simultaneously. This creates a throughput bottleneck, constraining execution speed regardless of CPU speed.
Primary Use Cases: Standard general-purpose personal computers (PCs), laptops, and general servers.
Harvard Architecture
Core Concept: Uses physically separate memory units and separate bus systems (address and data buses) for instructions and data.
Key Advantage: Enables concurrent memory access—the CPU can fetch the next instruction from instruction memory while simultaneously reading or writing data to data memory.
Primary Use Cases: Digital Signal Processors (DSPs), Microcontrollers (e.g., ARM Cortex-M, AVR, PIC), and modern internal CPU cache architectures (where L1 instruction cache and L1 data cache are split on Harvard principles).
2. The Instruction Cycle & CPU Execution Pipeline
The instruction cycle represents the sequence of basic operations performed by the CPU to execute a single program instruction:
+---------------+ +---------------+ +---------------+ +---------------+
| Fetch | --> | Decode | --> | Execute | --> | Store / |
| Instruction | | Opcode | | Operation | | Writeback |
+---------------+ +---------------+ +---------------+ +---------------+
Fetch (IF): The Program Counter (PC) holds the memory address of the next instruction. The CPU fetches the instruction from main memory/cache via the address bus and loads it into the Instruction Register (IR). The PC is then incremented to point to the next instruction.
Decode (ID): The Control Unit (CU) decodes the operational code (opcode) stored in the IR, identifies required operands, and reads operand values from registers or flags effective memory addresses.
Execute (EX): The Arithmetic Logic Unit (ALU) carries out the required arithmetic or logical calculation, or branches to a different address.
Store / Writeback (WB): Writes the resulting output back to a designated register or memory address location.
3. Addressing Modes
Addressing modes define the rules used by an instruction opcode to interpret operand fields and determine the Effective Address (EA) of data.
Immediate Addressing Mode: The operand is explicitly part of the instruction itself, meaning an effective address calculation is not needed (e.g.,
ADD 5). It is extremely fast, though limited by opcode bit length, and is typically used for initializing constants.Direct (Absolute) Addressing Mode: The instruction contains the exact memory address of the operand ($EA = A$, e.g.,
LOAD 2000). It is simple and requires exactly one memory reference to access data.Indirect Addressing Mode: The address field points to a memory location that contains the true effective address ($EA = [A]$, e.g.,
LOAD (2000)). While flexible, it requires two memory references, making execution slower.Register Direct Addressing Mode: The operand is stored directly in a specified CPU register ($EA = R$, e.g.,
ADD R1, R2). It is extremely fast because it requires no main memory access.Register Indirect Addressing Mode: A specified register contains the main memory address of the operand ($EA = [R]$, e.g.,
LOAD (R1)). This mode is highly useful for pointer operations and array traversals.Displacement / Base-Register Addressing Mode: The effective address is calculated by adding a register value to a displacement offset ($EA = [R] + \text{offset}$, e.g.,
LOAD R1, 100(R2)). It is heavily used in array indexing, structure parsing, and position-independent code.Relative (PC-Relative) Addressing Mode: The effective address is calculated relative to the current Program Counter value ($EA = PC + \text{offset}$, e.g.,
JMP +12). This is common in conditional branching and relocatable code.
4. Memory Hierarchy & Locality of Reference
Modern memory hierarchies balance capacity, access speed, and cost to deliver optimal average performance.
The Hierarchy Pyramid (Fastest to Slowest)
Registers: Internal CPU storage with sub-nanosecond, zero wait-state access.
Cache Memory (L1, L2, L3): Fast SRAM-based memory built directly onto or near the CPU die (1–10 ns access time).
Main Memory (RAM): DRAM-based storage used for active programs and operating system states (10–100 ns access time).
Secondary Storage (SSD / NVMe / HDD): Non-volatile flash or magnetic storage (microseconds to milliseconds access time).
Tertiary Storage: Magnetic tape or cloud cold storage (seconds to minutes access time).
Principle of Locality
Cache systems operate effectively because software exhibits two distinct patterns of memory access:
Temporal Locality: If a memory location is accessed once, it is highly likely to be accessed again in the near future (e.g., loop variables inside a
fororwhileloop).Spatial Locality: If a memory location is accessed, nearby memory locations are likely to be accessed soon after (e.g., contiguous elements in an array or sequential code instructions).
5. Digital Logic: Gates, Combinational, & Sequential Circuits
All computer hardware is constructed from basic logic gate primitives.
Universal Gates
NAND and NOR gates are designated as Universal Gates because any Boolean logic function (AND, OR, NOT, XOR) can be built using only NAND gates or only NOR gates.
Combinational Circuits
Outputs depend strictly on current inputs with no built-in memory or feedback loops:
Adders:
Half Adder: Adds two single-bit inputs; outputs $\text{Sum} = A \oplus B$ and $\text{Carry} = A \cdot B$.
Full Adder: Adds three single-bit inputs (including a Carry-in signal); outputs a Sum and a Carry-out signal.
Multiplexer (MUX): Known as a "Data Selector." It routes 1 of $2^n$ input data lines to a single output line using $n$ selection lines.
Demultiplexer (DEMUX): Takes a single input line and routes it to 1 of $2^n$ output lines using $n$ selection lines.
Decoder: Converts an $n$-bit binary input code into a maximum of $2^n$ unique output signals (frequently used in memory address decoding).
Encoder: Performs the inverse of a decoder, converting $2^n$ inputs back into an $n$-bit coded output.
Sequential Circuits
Outputs depend on current inputs AND the previous state using internal memory elements and feedback paths:
Flip-Flops: The fundamental 1-bit memory element (SR, JK, D, and T flip-flops).
D Flip-Flop: Used primarily for data storage and CPU registers.
T Flip-Flop: Used for counters, toggling state on clock edges.
Registers: Cascaded arrays of flip-flops used for temporary parallel or serial bit storage.
Counters: Sequential circuits designed to step through a deterministic sequence of binary states upon receiving clock pulses.
6. Pipeline Architecture & Hazards
Pipelining overlaps the execution of multiple instructions to increase overall instruction throughput without necessarily reducing the time required for a single instruction.
Pipeline Hazards (Performance Disruptions)
Structural Hazards: Occur when hardware resource conflicts arise because two or more instructions require the same physical component simultaneously (e.g., trying to fetch a new instruction while reading data from a single memory port).
Data Hazards: Occur when an instruction depends on the output of a preceding instruction that has not yet completed execution:
RAW (Read-After-Write): True data dependency (most common).
WAR (Write-After-Read): Anti-dependency.
WAW (Write-After-Write): Output dependency.
Control Hazards (Branch Hazards): Caused by conditional or unconditional branch instructions where the next target address is unknown during the fetch phase. These are handled using Branch Prediction or Delay Slots.
7. Flynn’s Classification of Parallel Architectures
Michael J. Flynn categorized computer architectures based on the number of concurrent instruction streams and data streams:
SISD (Single Instruction, Single Data): Standard single-core legacy computers executing one stream of instructions on one stream of data.
SIMD (Single Instruction, Multiple Data): A single instruction operates on multiple data items simultaneously. Found in GPUs, vector processors, and modern CPU multimedia extensions (e.g., AVX).
MISD (Multiple Instruction, Single Data): Multiple instructions operate on a single data stream. Primarily theoretical or used in specialized fault-tolerant systems (e.g., space flight controls).
MIMD (Multiple Instruction, Multiple Data): Multiple independent processors execute different instructions on different data streams. Modern multi-core CPUs, distributed clusters, and supercomputers belong to this class.
Top 50+ Important MCQs for Bihar STET & BPSC
Who is known as the father of modern computer architecture?
Answer: John Von Neumann
Which of the following circuit is used to store 1 bit of data?
Answer: Flip-Flop
Which memory is the fastest in a computer system?
Answer: Register
The basic building block of any digital circuit is:
Answer: Logic Gate
Which logic gates are called Universal Gates?
Answer: NAND and NOR gates
Which component decodes the instruction and controls the data flow inside the CPU?
Answer: Control Unit (CU)
A circuit that converts $2^n$ input lines into a single output line is known as:
Answer: Multiplexer (MUX)
A circuit that converts binary information from $n$ input lines to a maximum of $2^n$ unique output lines is called:
Answer: Decoder
In which addressing mode is the operand explicitly given within the instruction itself?
Answer: Immediate Addressing Mode
The program counter (PC) register stores:
Answer: The address of the next instruction to be executed.
Instruction Register (IR) holds:
Answer: The instruction currently being executed.
What does DMA stand for in computer architecture?
Answer: Direct Memory Access
Main function of Direct Memory Access (DMA) controller is:
Answer: Transferring data directly between I/O devices and main memory without constantly involving the CPU.
RISC stands for:
Answer: Reduced Instruction Set Computer
CISC stands for:
Answer: Complex Instruction Set Computer
In pipeline architecture, maximum throughput is achieved when:
Answer: All pipeline stages take equal execution time.
Which hazard occurs when an instruction depends on the result of a previous instruction?
Answer: Data Hazard
Cache memory works on which principle?
Answer: Locality of Reference (Temporal and Spatial Locality)
What happens when the CPU requests data and it is found in the cache?
Answer: Cache Hit
What happens when the requested data is not found in the cache memory?
Answer: Cache Miss
Main Memory (RAM) is composed of:
Answer: Dynamic RAM (DRAM) chips
Which memory requires periodic refreshing to retain data?
Answer: DRAM (Dynamic RAM)
SRAM (Static RAM) is primarily built using:
Answer: Flip-Flops
Which register holds the memory location address where read/write operation is to be performed?
Answer: MAR (Memory Address Register)
Which register temporarily holds data read from or written to memory?
Answer: MDR (Memory Data Register) / MBR (Memory Buffer Register)
Which complement representation is used by most modern computers for binary subtraction?
Answer: 2's Complement
What is the 2's complement of binary number
1010?Answer:
0110
A full adder circuit adds how many binary bits at a time?
Answer: 3 bits (2 inputs + 1 carry-in)
A half adder circuit consists of which two logic gates?
Answer: XOR gate (for Sum) and AND gate (for Carry)
Which bus is unidirectional in a standard microprocessor system?
Answer: Address Bus
Which bus is bidirectional?
Answer: Data Bus
A 32-bit microprocessor can address how much memory directly with a 32-bit address bus?
Answer: $2^{32}$ bytes = $4\text{ GB}$
Von Neumann architecture relies on which key concept?
Answer: Stored-Program Concept
In vector processing, instructions operate on:
Answer: Arrays of data (Vectors) rather than single scalar values.
According to Flynn's taxonomy, standard single-processor PCs belong to:
Answer: SISD (Single Instruction, Single Data)
Modern multi-core processors typically belong to which Flynn's classification?
Answer: MIMD (Multiple Instruction, Multiple Data)
Which cache mapping technique allows a main memory block to be placed in any cache line?
Answer: Fully Associative Mapping
Which cache mapping technique restricts a memory block to exactly one specific line in the cache?
Answer: Direct Mapping
What is the purpose of a Interrupt Service Routine (ISR)?
Answer: A software routine executed by the CPU in response to an interrupt signal.
Polled I/O is also referred to as:
Answer: Programmed I/O
Which interrupt cannot be ignored or disabled by the CPU?
Answer: Non-Maskable Interrupt (NMI)
Stack Pointer (SP) points to:
Answer: The top location of the stack memory.
Data structure used in implementation of function calls and subroutines in CPU registers is:
Answer: LIFO / Stack
Which memory is non-volatile in nature?
Answer: ROM (Read Only Memory), Hard Disk, Flash Memory
Which ROM type can be erased using Ultraviolet (UV) light?
Answer: EPROM (Erasable Programmable ROM)
Which ROM type can be erased electrically bit-by-bit or block-wise?
Answer: EEPROM
Hard disk drive tracks are divided into smaller structural units called:
Answer: Sectors
In direct memory access (DMA), cycle stealing mode means:
Answer: DMA controller takes control of the bus for transferring 1 byte/word and then returns control to the CPU.
Booth's Algorithm is used for:
Answer: Fast multiplication of signed binary numbers.
Restoring and Non-Restoring algorithms are used for:
Answer: Binary Division
The Boolean expression for an XOR gate with inputs A and B is:
Answer: $A \bar{B} + \bar{A} B$ (or $A \oplus B$)
A circuit that converts $n$ input lines to 1 output line using select lines requires how many select lines?
Answer: $\log_2(n)$ select lines
