High-Yield Revision Notes (Quick Theory)
1. Computer System Hardware Architecture
Modern computers Von Neumann Architecture par kaam karte hain jisme Program Instructions aur Data dono same memory space me store hote hain.
Central Processing Unit (CPU):
ALU (Arithmetic Logic Unit): Mathematical (+, -, *) aur Logical (AND, OR, NOT) operations execute karta hai.
Control Unit (CU): System ke sare hardware component signals ko coordinate aur control karta hai.
Special CPU Registers:
Program Counter (PC): Next execute hone wale instruction ka address hold karta hai.
Instruction Register (IR): Memory se fetch kiye gaye current instruction ko hold karta hai.
MAR (Memory Address Register): Memory access hone wale location ka physical address hold karta hai.
MDR / MBR (Memory Data/Buffer Register): Memory se read ya write kiye ja rahe data ko holding area me rakhta hai.
Accumulator (AC): ALU ke immediate calculation results ko hold karta hai.
System Buses:
Address Bus: Unidirectional (CPU $\rightarrow$ Memory/IO). Address width ($N$ bits) se memory size define hota hai ($2^N$).
Data Bus: Bidirectional (CPU $\leftrightarrow$ Memory/IO). Data transfer karta hai.
Control Bus: Control signals transfer karta hai (Read, Write, Interrupt, Clock).
2. Instruction Cycle & Pipelining
Instruction Cycle Flow: Fetch $\rightarrow$ Decode $\rightarrow$ Read Effective Address $\rightarrow$ Execute $\rightarrow$ Write Back / Store Result.
Instruction Pipelining: Multiple instructions ki processing stages ko overlap karke execution speed badhane ki technique.
Ideal speedup of $k$-stage pipeline = $k$ times.
Hazards (Performance Bottlenecks):
Structural Hazard: Jab 2 instructions ko same hardware resource simultaneously chahiye hota hai.
Data Hazard: Dependency issue (e.g., RAW - Read After Write).
Control/Branch Hazard: Branching or conditional jump instructions ke karan hone wale stalls.
3. Control Unit: Hardwired vs Microprogrammed
| Feature | Hardwired Control Unit | Microprogrammed Control Unit |
| Implementation | Fixed Logic Gates, Flip-Flops, Decoders. | Microinstructions in Control Memory (ROM). |
| Speed | Extremely Fast (Direct Circuit Propagation). | Slower (Control memory lookup required). |
| Flexibility | Difficult to modify/redesign. | Easily upgradable by updating microcode. |
| Architecture | Preferred in RISC architectures. | Preferred in CISC architectures. |
4. Memory Hierarchy & Cache Mapping
Hierarchy: Registers $>$ Cache (SRAM) $>$ Main Memory (DRAM) $>$ Secondary Storage (SSD/HDD).
Cache Mapping Techniques:
Direct Mapping: Har Main Memory block strictly ek particular Cache Line me hi map ho sakta hai. ($\text{Line} = \text{Block} \bmod \text{Total Lines}$). High conflict miss rate.
Fully Associative Mapping: Block Cache ke kisi bhi free line me store ho sakta hai. No conflict misses; costly hardware logic needed.
Set-Associative Mapping: Cache sets me divided hota hai. Block assigned set ke kisi bhi line me map ho sakta hai. ($\text{Set} = \text{Block} \bmod \text{Total Sets}$).
5. Input/Output (I/O) Transfer Modes
Programmed I/O: CPU continuously I/O device ka status check (polling) karta hai. High CPU idle time.
Interrupt-Driven I/O: Device ready hone par CPU ko hardware interrupt bhejta hai. CPU context switch karke Interrupt Service Routine (ISR) execute karta hai.
Direct Memory Access (DMA): Dedicated DMA controller without CPU intervention memory aur I/O ke beech direct high-speed data transfer karta hai.
Burst Mode: Pure data block ko ek saath bina bus release kiye transfer karta hai.
Cycle Stealing Mode: Single word/byte transfer ke liye ek clock cycle steal karta hai.
Part 2: Top 30 Important MCQs (With Solutions)
CPU ka kaun sa register next execute hone wale instruction ka address hold karta hai?
Answer: Program Counter (PC)
System bus me kaun sa bus strictly Unidirectional hota hai?
Answer: Address Bus
In a 16-bit address bus, total kitne memory locations ko directly address kiya ja sakta hai?
Answer: $2^{16} = 65,536$ locations ($64\text{ KB}$)
Zero-Address Instruction format me operations kis data structure ka use karke perform kiye jate hain?
Answer: Stack (
PUSHaurPOPoperations)
Direct Cache Mapping me Memory Block $13$ total $4$ Cache Lines me kis line index par map hoga?
Answer: Line $1$ ($13 \bmod 4 = 1$)
Cache Hit ka matlab kya hota hai?
Answer: Jab CPU dwara requested data direct Cache memory me mil jaye.
SRAM (Static RAM) aur DRAM (Dynamic RAM) me mukhya antar kya hai?
Answer: SRAM Flip-Flops se banta hai aur fast hota hai, jabki DRAM Capacitors se banta hai aur periodic refresh ki zaroorat hoti hai.
Booth's Algorithm kis operation ke hardware implementation ke liye use hota hai?
Answer: Signed Binary Multiplication (2's complement representation)
RISC (Reduced Instruction Set Computer) ki sabse mukhya visheshata kya hai?
Answer: Simple, fixed-length instructions aur Memory access strictly
LOADaurSTOREse hota hai.
Hardwired Control Unit ki sabse badi khubi kya hai?
Answer: High Execution Speed (bina kisi microcode lookup latency ke).
DMA transfer me jab controller continuously pure data block ko bina bus release kiye send karta hai, use kya kehte hain?
Answer: Burst Mode (ya Block Transfer Mode)
RAW (Read-After-Write) Hazard ko aur kis naam se jana jata hai?
Answer: True Data Dependency
Interrupt Service Routine (ISR) ka initial starting address kahan se milta hai?
Answer: Interrupt Vector Table (IVT)
Write-Through Cache Policy me update kaise hota hai?
Answer: Data Cache aur Main Memory dono me simultaneously write/update hota hai.
Write-Back Policy me Main Memory kab update hota hai?
Answer: Jab modified cache line ko overwrite/replace (evict) kiya jata hai.
Stack-based execution architecture me operand explicit specifications ki zaroorat kyun nahi hoti?
Answer: Kyunki Top of Stack (TOS) implicit operand hota hai.
Which microinstruction format doesn't require decoders and offers maximum speed?
Answer: Horizontal Microinstruction (unencoded control signals)
Pipeline me Branch / Jump Instructions ke karan hone wale delays ko kya kehte hain?
Answer: Control Hazards (ya Branch Hazards)
CPU dwara Arithmetic result me Overflow detect karne ke liye kis flag register ka use hota hai?
Answer: Overflow Flag (OF)
Interrupt jise CPU dwara disable ya ignore nahi kiya ja sakta, use kya kehte hain?
Answer: Non-Maskable Interrupt (NMI)
Daisy Chaining method kis purpose ke liye use hoti hai?
Answer: Bus Arbitration (Priority-based Bus Allocation)
2's complement system me $-8$ ko 4-bit binary me kaise represent karenge?
Answer:
1000
Data bus ki width CPU ki kis capacity ko determine karti hai?
Answer: Single cycle me transfer hone wale word length (8-bit, 32-bit, 64-bit) ko.
Which Cache Mapping provides zero conflict miss?
Answer: Fully Associative Mapping
Control Memory (ROM) me store hone wale individual sequence operations ko kya kehte hain?
Answer: Microprogram / Microinstructions
Address Decoding circuit me $N$ input lines kitne output selection lines me decode hote hain?
Answer: $2^N$ selection lines
Programmed I/O me CPU ka kaun sa sabse bada drawback hota hai?
Answer: CPU Polling Loop (busy waiting) me time waste hota hai.
Accumulator (AC) register ka mukhya kaam kya hai?
Answer: ALU ke dwara kiye gaye intermediate results ko temporarily hold karna.
32-bit Address Bus wala System maximum kitni Main Memory address kar sakta hai?
Answer: $2^{32} \text{ bytes} = 4 \text{ GB}$
Instructions ke Fetch, Decode aur Execute phases ko overlap karne ki technique ko kya kehte hain?
Answer: Instruction Pipelining
